The present invention relates generally to semiconductor device manufacturing and, more particularly, to a transistor device having non-relaxed, embedded stressors with solid source outdiffused extension regions.
The gain of a metal oxide semiconductor (MOS) transistor, usually defined by the transconductance (gm), is proportional to the mobility (μ) of the majority carrier in the transistor channel. The current carrying capability, and hence the performance of an MOS transistor, is proportional to the mobility of the majority carrier in the channel. The mobility of holes, which are the majority carriers in a P-channel field effect (PFET) transistor, and the mobility of electrons, which are the majority carriers in an N-channel field effect (NFET) transistor, may be enhanced by applying an appropriate stress to the channel. Existing stress engineering methods greatly enhance circuit performance by increasing device drive current without increasing device size and device capacitance. For example, a tensile stress liner layer formed over an NFET transistor induces a longitudinal stress in the channel and enhances the electron mobility. Conversely, a compressive stress liner formed over a PFET transistor induces a compressive stress in the channel and enhances the hole mobility.
In lieu of (or in addition to) stress liner layers, embedded source and drain regions may be epitaxially grown adjacent an FET channel, such as by removing portions of a semiconductor substrate material (e.g., silicon) and then regrowing a different semiconductor material in the recesses adjacent the channel. In the case of an NFET device, such an embedded stressor material may be silicon carbon (Si:C) for example, while in the case of a PFET device, such an embedded stressor material may be silicon germanium (SiGe) for example. With either approach (liner layer or embedded stressors), the resulting enhanced carrier mobility, in turn, leads to higher drive currents and therefore higher circuit level performance.
The continuous scaling of transistor devices has produced a series of difficult challenges to the processes used to form the active layers in deep sub-micron transistors. Two major requirements in the downsizing of MOSFETs are the suppression of “off” state leakage currents, and low resistance for a high current drive in the “on” state. In small gate lengths even when the device is in the “off” state, a leakage current from the drain to the source is observed due to the lowering of the threshold voltage (VT) as gate length is decreased. The space charge region near the drain may also touch the source somewhere deeper in the substrate where the gate bias cannot control the potential and punch through occurs at smaller drain biases. The off current is a key design parameter and can be minimized by keeping the junctions shallow.
However, ion implantation to form ultra-shallow junctions (e.g., less than about 300 Angstroms) is increasingly difficult to control. For example, higher dopant implant concentrations are required to avoid an increase in parasitic resistances at shallower junction depths. While reducing the ion implant energy may result in shallower junctions, the higher required dopant concentration required contributes to significant semiconductor substrate damage including forming amorphous or disordered lattice regions. Consequently, solid source diffusion is an alternative approach to forming source/drain junction regions. Here, a solid phase diffusion source layer is formed on a substrate, followed by an annealing step (e.g., rapid thermal anneal, laser anneal, spike anneal) to diffuse the dopant impurities within the diffusion source layer.
Accordingly, the semiconductor industry continually faces challenges with regard to maintaining good carrier mobility, as well as forming shallow junctions as the devices continue to scale.